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this product conforms to specifications per the terms of the ramtron ramtron international corporation s tandard warranty . the product has completed ramtron s internal 1850 ramtron drive, colorado springs, co 80921 qualification testing and has reached production status. (800) 545 - fram, (719) 481 - 7000 www.ramtron.com rev. 3.0 jan. 2012 page 1 of 14 fm 25l04b 4kb serial 3v f - ram memory features 4k bit ferroelectric nonvolatile ram ? organized as 512 x 8 bits ? high endurance 100 trillion (10 14 ) read/write s ? 38 year data retention ( @ +75oc) ? nodelay? writes ? advanced high - reliabil ity ferroelectric process very fast serial peripheral interface - spi ? up to 20 mhz frequency ? direct hardware replacement for eeprom ? spi mode 0 & 3 (cpol, cpha=0,0 & 1,1) sophisticated write protection scheme ? hardware protection ? software protection l ow power consumption ? low voltage operation 2.7 - 3.6v ? 200 ? a active current (1 mhz) ? 3 ? a (typ.) standby current industry standard configuration ? industrial temperature - 40 ? c to +85 ? c ? 8 - pin green/rohs soic and tdfn packages description the fm 25l04b is a 4 - kilobit nonvolatile memory employing an advanced ferroelectric process. a ferroelectric random access memory or f - ram is nonvolatile and performs reads and writes like a ram. it provides reliable data retention for 38 year s while eliminating the complex ities, overhead, and system level reliability problems caused by eeprom and other nonvolatile memories. t he fm 25l04b performs write operations at bus speed. no write delays are incurred. data is written to the m emory array immediately after each byte has been transferred to the device. the next bus cycle may commence without the need for data polling. the fm25l04b is capable of supporting 10 14 read/write cycles, or a million times more write cycles than eeprom . these capabilities make the fm 25l04b ideal for nonvolatile memory applications requiring frequent or rapid writes or low power operation. examples range from data collection, where the number of write cycles may be critical, to demanding industrial controls where the long write time of eeprom can cause data loss. the fm 25l04b provides substantial benefits to users of serial eeprom as a hardware drop - in replacement. the fm 25l04b uses the high - speed spi bus, which enhances the high - speed write capability of f - ram technology. device specifications a re guaranteed over an industrial temperature range of - 40c to +85c. pin configuration pin name function /cs chip select /wp write protect /hold hold sck serial clock si serial data input so serial data output vdd supply voltage vss ground ordering information fm25l04b - g green/rohs 8 - pin soic fm25l04b - gtr green/rohs 8 - pin soic, tape & reel fm25l04b - dg green/rohs 8 - pin tdfn fm25l04b - d gtr green/rohs 8 - pin tdfn, tape & reel /cs so /wp vss vdd /hold sck si 8 7 6 5 1 2 3 4 top view cs so wp vss vdd hold sck si 1 2 3 4 8 7 6 5
fm25l04b - 4kb 3v spi f - ram rev. 3.0 jan. 2012 page 2 of 14 figure 1. block diagram pin descriptions pin name i/o description /cs input chip select: this active low input activates the device. when high, the device enters low - power standby mode, ignores other inputs, and all outputs are tri - stated. when low, the device internally activates the sck signal. a falling edge on /cs must occur prior to every op - code. sck input serial clock: all i/o activity is synchronized to the serial clock. inputs are latched on the rising edge and outputs occur on the fa lling edge. since the device is static, the clock frequency may be any value between 0 and 20 mhz and may be interrupted at any time. /hold input hold: the /hold pin is used when the host cpu must interrupt a memory operation for another task. when /hold is low, the current operation is suspended. the device ignores any transition on sck or /cs. all transitions on /hold must occur while sck is low. /wp input write protect: this active low pin prevents write operations to the memory array or the status register. a complete explanation of write protection is provided below. si input serial input: all data is input to the device on this pin. the pin is sampled on the rising edge of sck and is ignored at other times. it should always be driven to a valid logic level to meet idd specifications. * si may be connected to so for a single pin data interface. so output serial output: this is the data output pin. it is driven during a read and remains tri - stated at all other times including when /hold is low. data transitions are driven on the falling edge of the serial clock. * so may be connected to si for a single pin data interface. vdd supply power supply (2.7v to 3.6 v) vss supply ground instruction decode clock generator control logic write protect instruction register address register counter 64 x 64 fram array 9 data i / o register 8 nonvolatile status register 3 wp cs hold sck so si
fm25l04b - 4kb 3v spi f - ram rev. 3.0 jan. 2012 page 3 of 14 overview the fm 25l04b is a serial f - ram memory. the memory arra y is logically organized as 512 x 8 and is accessed using an industry standard serial peripheral interface or spi bus. functional operation of the f - ram is similar to serial eeproms. the major difference between the fm 25l04b and a serial eeprom with the sa me pinout is the f - ram s superior write performance and power consumption. memory architecture when accessing the fm 25l04b , the user addresses 512 locations of 8 data bits each. these data bits are shifted serially. the addresses are accessed using the sp i protocol, which includes a chip select (to permit multiple devices on the bus), an op - code, and an address. the upper address bit is included in the op - code. the complete address of 9 - bits specifies each byte address uniquely. most functions of the fm 2 5l04b either are controlled by the spi interface or are handled automatically by on - board circuitry. the access time for memory operation is essentially zero, beyond the time needed for the serial protocol. that is, the memory is read or written at the spe ed of the spi bus. unlike an eeprom, it is not necessary to poll the device for a ready condition since writes occur at bus speed. so, by the time a new bus transaction can be shifted into the device, a write operation will be complete. this is explained i n more detail in the interface section. users expect several obvious system benefits from the fm 25l04b due to its fast write cycle and high endurance as compared with eeprom. in addition there are less obvious benefits as well. for example in a high nois e environment, the fast - write operation is less susceptible to corruption than an eeprom since it is completed quickly. by contrast, an eeprom requiring milliseconds to write is vulnerable to noise during much of the cycle. note that the fm 25l04b contain s no power management circuits other than a simple internal power - on reset. it is the users responsibility to ensure that v dd is within datasheet tolerances to prevent incorrect operation. it is recommended that the part is not powered down with chip ena ble active. serial peripheral interface C spi bus the fm 25l04b employs a serial peripheral interface (spi) bus. it is specified to operate at speeds up to 20 mhz. this high - speed serial bus provides high performance serial communication to a host microcon troller. many common microcontrollers have hardware spi ports allowing a direct interface. it is quite simple to emulate the port using ordinary port pins for microcontrollers that do not. the fm 25l04b operates in spi mode 0 and 3. the spi interface uses a total of four pins: clock, data - in, data - out, and chip select. a typical system configuration uses one or more fm 25l04b devices with a microcontroller that has a dedicated spi port, as figure 2 illustrates. note that the clock, data - in, and data - out pin s are common among all devices. the chip select and hold pins must be driven separately for each fm 25l04b device. for a microcontroller that has no dedicated spi bus, a general purpose port may be used. to reduce hardware resources on the controller, it is possible to connect the two data pins (si, so) together and tie off (high) the /hold pin. figure 3 shows a configuration that uses only three pins . protocol overview the spi interface is a synchronous serial interface using clock and data pins. it is i ntended to support multiple devices on the bus. each device is activated using a chip select. once chip select is activated by the bus master, the fm 25l04b will begin monitoring the clock and data lines. the relationship between the falling edge of /cs, th e clock and data is dictated by the spi mode. the device will make a determination of the spi mode on the falling edge of each chip select. while there are four such modes, the fm 25l04b supports m odes 0 and 3. figure 4 shows the req uired signal relationshi ps for m odes 0 and 3. for both modes, data is clocked into the fm 25l04b on the rising edge of sck and data is expected on the first rising edge after /cs goes active. if the clock begins from a high state, it will fall prior to beginning data transfer in order to create the first rising edge. the spi protocol is controlled by op - codes. these op - codes specify the commands to the device. after /cs is activated the first byte transferred from the bus master is the op - code. following the op - code, any addres ses and data are then transferred. note that the wren and wrdi op - codes are commands with no subsequent data transfer. important: the /cs must go inactive (high) after an operation is complete and before a new op - code can be issued. there is one valid op - code only per active chip select.
fm25l04b - 4kb 3v spi f - ram rev. 3.0 jan. 2012 page 4 of 14 figure 2. system configuration with spi port figure 3. system configuration without spi port spi mode 0: cpol=0, cpha=0 spi mode 3 : cpol=1, cpha=1 figure 4. spi modes 0 & 3 spi microcontroller fm 25 l 04 b so si sck cs hold fm 25 l 04 b so si sck cs hold sck mosi miso ss 1 ss 2 hold 1 hold 2 mosi : master out slave in miso : master in slave out ss : slave select m i c r o c o n t r o l l e r f m 2 5 l 0 4 b s o s i s c k c s h o l d p 1 . 0 p 1 . 1 p 1 . 2 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
fm25l04b - 4kb 3v spi f - ram rev. 3.0 jan. 2012 page 5 of 14 data transfer all data transfers to and from the fm 25l04b occur in 8 - bit groups. they are synchronized to the clock signal (sck), and they transfer most significant bit (msb) first. seri al inputs are registered on the rising edge of sck. outputs are driven from the falling edge of sck. command structure there are six commands called op - codes that can be issued by the bus master to the fm 25l04b . they are listed in the table below. these op - codes control the functions performed by the memory. they can be divided into three categories. first, there are commands that have no subsequent operations. they perform a single function such as to enable a write operation. second are commands follow ed by one byte, either in or out. they operate on the status register. the third group includes commands for memory transactions followed by address and one or more bytes of data. table 1. op - code commands name description op - code wren set write enable latch 0000 0110b wrdi write disable 0000 0100b rdsr read status register 0000 0101b wrsr write status register 0000 0001b read read memory data 0000 a011b write write memory data 0000 a010b wren - set write enable latch the fm 25l04b will power up with writes disabled. the wren command must be issued prior to any write operation. sending the wren op - code will allow the user to issue subsequent op - codes for write operations. these include writing the status register and writing the memory. sending the wren op - code causes the internal write enable latch to be set. a flag bit in the status register, called wel, indicates the state of the latch. wel=1 indicates that writes are permitted. attempting to write the wel bit in the status register has no eff ect. completing any write operation will automatically clear the write - enable latch and prevent further writes without another wren command. figure 5 below illustrates the wren command bus configuration. wrdi - write disable the wrdi command disables all write activity by clearing the write enable latch. the user can verify that writes are disabled by reading the wel bit in the status register and verifying that wel=0. figure 6 illustrates the wrdi command bus configuration. f igure 5. wren bus configuration figure 6. wrdi bus configuration hi-z 0 1 2 3 4 5 6 7 0 0 0 0 0 1 1 0 cs sck si so cs sck si so hi-z 0 1 2 3 4 5 6 7 0 0 0 0 0 1 0 0
fm25l04b - 4kb 3v spi f - ram rev. 3.0 jan. 2012 page 6 of 14 rdsr - read status register the rdsr command allows the bus master to verify the contents of the status register. reading s tatus provides information about t he current state of the write protection features. following the rdsr op - code, the fm 25l04b will return one byte w ith the contents of the status register. the status r egister is described in detail in a later section. wrsr C write status register the wrs r command allows the user to select certain write protection features b y writing a byte to the status r egister. prior to issuing a wrsr command, the /wp pin must be high or inactive. prior to sending the wrsr command, the user must send a wren command to e nable writes. note that executing a wrsr command is a write operation and therefore clears the write enabl e latch. figure 7. rdsr bus configuration figure 8. wrsr bus configuration (wren not shown) status register & write protection the write protection features of the fm 25l04b are multi - tiered. taking the /wp pin to a logic low state is the hardware write protect function. all write operations are blocked when /wp is low. to write the memory with /wp high, a wren op - code must first be issued. assuming that writes are enabled using wren and by /wp, writes to memory are controlled by the status register . as described above, writes to the status register are performed using the wrsr command and subj ect to the /wp pin. the status r egister is organ ized as follows. table 2. status register bit 7 6 5 4 3 2 1 0 name 0 0 0 0 bp1 bp0 wel 0 bits 0 and 7 - 4 are fixed at 0 and cannot be modified. note that bit 0 ( ready in eeproms) is unnecessary as the f - ram writes in real - time and is never busy. the b p1 and bp0 control write protection features. they are nonvolatile (shaded yellow). the wel flag indicates the state of the write enable latch. attempting to dir ectly write the wel bit in the s tatus r egister has no effect on its state. this bit is internal ly set and cleared via the wren and wrdi commands, respectively. bp1 and bp0 are memory block write protection bits. they specify po rtions of memory that are write - protected as shown in the following table. table 3. block memory write protection bp1 bp 0 protected address range 0 0 none 0 1 180h to 1ffh (upper ?) 1 0 100h to 1ffh (upper ?) 1 1 000h to 1ffh (all) the bp1 and bp0 bits allo w software to selectively write - protect the array. these settings are only used when the /wp pin is inactive and the wren command has been issued. the following table summarizes the write protection conditions.
fm25l04b - 4kb 3v spi f - ram rev. 3.0 jan. 2012 page 7 of 14 table 4. write protection wel /wp protected blocks unprotected blocks status register 0 x protected protected protected 1 0 protected protected protected 1 1 protected unprotected unprotected memory operation the spi interface, which is capable of a relatively high clock frequency, highlights the fast write capability of the f - ram technology. unlike spi - bus eeproms, the fm 25l04b can perform sequential w rites at bus speed. no page register is needed and any number of sequential writes may be performed. write operation all writes to the memory array begin with a wren op - code. the next op - code is the write instruction. this op - code must include the addres s msb. it is followed by a single byte address value. in total, the 9 - bits specify the address of the first byte of the write operation. subsequent bytes are data and they are written sequentially. addresses are incremented internally as long as the bus ma ster continues to issue clocks. if the last address of 1ffh is reached, the counter will roll over to 000h. data is written msb first. a write operation is shown in figure 9. unlike eeproms, any number of bytes can be written sequentially and each byte is written to memory immediately after it is clocked in (after the 8 th clock). the rising edge of /cs terminates a write op - code operation. asserting /wp active in the middle of a write operation will have no e ffect until the byte being written has completed . read operation after the falling edge of /cs, the bus master can issue a read op - code. this op - code must include the address msb. it is followed by a single byte address value. in total, the 9 - bits specify the address of the first byte of the read oper ation. after the op - code and address are complete, the si line is ignored. the bus master issues 8 clocks, with one bit read out for each. addresses are incremented internally as long as the bus master continues to issue clocks. if the last address of 1ffh is reached, the counter will roll over to 000h. data is read msb first. the rising edge of /cs terminates a read op - code operation. a read operation is shown in figure 10. hold the /hold pin can be used to interrupt a serial operation without aborting i t. if the bus master pulls the /hold pin low while sck is low, the current operation will pause. taking the /hold pin high while sck is low will resume an operation. the transitions of /hold must occur while sck is low, but the sck and /cs pins can toggle during a hold state. figure 9. memory write (wren not shown) figure 10. memory read c s s c k s i s o 0 1 2 3 4 5 6 7 0 0 h i - z 1 m s b l s b 0 1 2 3 4 6 7 a 7 0 o p - c o d e 8 - b i t a d d r e s s 0 a 0 a 3 a 4 a 5 a 6 0 1 2 3 4 5 6 7 7 d a t a i n 0 1 2 3 4 5 6 m s b l s b 7 0 0 0 a 8 a 1 a 2 5 c s s c k s i s o 0 1 2 3 4 5 6 7 0 0 h i - z 1 0 o p - c o d e 0 1 2 3 4 5 6 7 7 d a t a o u t 0 1 2 3 4 5 6 m s b l s b 7 0 1 0 0 a 8 m s b l s b 0 1 2 3 4 6 7 a 7 8 - b i t a d d r e s s a 0 a 3 a 4 a 5 a 6 a 1 a 2 5
fm25l04b - 4kb 3v spi f - ram rev. 3.0 jan. 2012 page 8 of 14 endurance the fm25l04b devices are capable of being accessed at least 10 14 times, reads or writes. an f - ram memory operates with a read and restore mechanism. therefore, an endurance cycle is applied on a row basis for each access (read or write) to the memory array. the f - ram architecture is based on an array of rows and columns. rows are defined by a8 - a 3 and column addresses by a2 - a0. see block diagram (pg 2) which shows the array as 64 rows of 64 - bits each. the entire row is internally accessed once whether a single byte or all eight bytes are read or written. each byte in the row is counted only once in an endurance calculation. the table below shows endurance calculations for 64 - byte repeating loop, which includes an op - code, a starting address, and a sequential 64 - byte data stream. this causes each byte to experience one endurance cycle through the loop. f - ram read and write endurance is virtually unlimited even at 20mhz clock rate . table 5. time to reach endurance limit for repeating 64 - byte loop sck freq (mhz) endurance cycles/sec. endurance cycles/year years to reach limit 20 37,31 0 1.18 x 1 0 12 85.1 10 18,660 5.88 x 10 1 1 170.2 5 9,33 0 2.94 x 10 1 1 340.3
fm25l04b - 4kb 3v spi f - ram rev. 3.0 jan. 2012 page 9 of 14 electrical specifications absolute maximum ratings symbol description ratings v dd power supply voltage with respect to v ss - 1.0v to +5.0v v in voltage on any pin with respect to v ss - 1.0v to +5.0v and v in < v dd +1.0v t stg storage temperature - 55 ? c to + 125 ? c t lead lead temperature (soldering, 10 seconds) 26 0 ? c v esd electrostatic discharge voltage - human body model (aec - q100 - 002 rev. e) - charged device model (aec - q100 - 011 rev. b) - machine model ( a ec - q100 - 003 rev. e ) 4kv 1.25kv 300v package moisture sensitivity level msl - 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and the functional ope ration of the device at these or any other conditions above those listed in the operational section of this specification is not implied. exposure to absolute maximum ratings conditions for extended periods may affect device reliabil ity. dc operating co nditions ( t a = - 40 ? c to + 85 ? c, v dd = 2.7v to 3.6 v unless otherwise specified) symbol parameter min typ max units notes v dd power supply voltage 2.7 3.3 3.6 v i dd vdd supply current @ sck = 1.0 mhz @ sck = 20 .0 mhz - - 0.2 3.0 ma ma 1 i sb stan dby current 3 6 ? a 2 i li input leakage current - ? 1 ? a 3 i lo output leakage current - ? 1 ? a 3 v ih input high voltage 0.7 v dd v dd + 0.3 v v il input low voltage - 0.3 0.3 v dd v v oh output high voltage @ i oh = - 2 ma v dd C 0.8 - v v ol output low voltage @ i ol = 2 ma - 0.4 v v hys input hysteresis 0.05 v dd - v 4 notes 1. sck toggling between v dd - 0.3v and v ss , other inputs v ss or v dd - 0.3v. 2. sck = si = /cs=v dd . all inputs v ss or v dd . 3. v ss ? v in ? v dd and v ss ? v out ? v dd . 4. this parameter is charact erized but not 100% tested. applies only to /cs and sck pins.
fm25l04b - 4kb 3v spi f - ram rev. 3.0 jan. 2012 page 10 of 14 ac parameters ( t a = - 40 ? c to + 85 ? c, v dd = 2.7v to 3.6v, c l = 30pf, unless otherwise specified) symbol parameter min max units notes f ck sck clock frequency 0 20 mhz t ch clock high time 22 ns 1 t cl clock low time 22 ns 1 t csu chip select setup 10 ns t csh chip select hold 10 ns t od output disable time 20 ns 2 t odv output data valid time 20 ns t oh output hold time 0 ns t d deselect time 60 ns t r data in rise time 50 ns 2,3 t f data in fall time 50 ns 2,3 t su data setup time 5 ns t h data hold time 5 ns t hs /hold setup time 10 ns t hh /hold hold time 10 ns t hz /hold low to hi - z 20 ns 2 t lz /hold high to data active 20 ns 2 notes 1. t ch + t cl = 1/f ck . 2. for clo ck high time t ch 35 ns, the parameter t odv is extended such that t ch + t odv 65 ns. 3. this parameter is characterized but not 100% tested. 4. rise and fall times measured between 10% and 90% of waveform. capacitance ( t a = 25 ? c, f=1.0 mhz, v dd = 3.3v) symbol parameter min max units notes c o output c apacitance (so) - 8 pf 1 c i input c apacitance - 6 pf 1 notes 1. this parameter is characterized but not 100% tested. 2. sl ope measured at any point on v dd waveform . ac test conditions input pulse levels 10% and 90% of v dd input r ise and fall times 5 ns input and output timing levels 0.5 v dd output load capacitance 30 pf data retention symbol parameter min max units notes t dr @ +85oc 10 - years @ +80oc 19 - years @ +75oc 38 - years
fm25l04b - 4kb 3v spi f - ram rev. 3.0 jan. 2012 page 11 of 14 serial data bus timing /hold timing power cycle timing power cycle timing ( t a = - 40 ? c to + 85 ? c , v dd = 2.7v to 3.6v unless otherwise specified ) symbol parameter min max units notes t pu v dd (min) to first access star t 1 0 - ms t pd last access complete to v dd (min) 0 - ? s t v r v dd rise time 3 0 - ? s/v 1 t vf v dd fall time 3 0 - ? s/v 1 notes 1. sl ope measured at any point on v dd waveform . cs sck si so 1 / tck tcl tch tcsh todv toh tod tcsu tsu th td tr tf cs sck so hold ths thh thz tlz ths thh v d d m i n t p u v d d c s t v r t p d t v f
fm25l04b - 4kb 3v spi f - ram rev. 3.0 jan. 2012 page 12 of 14 mechanical drawing 8 - pin soic (jedec standard ms - 012 variation aa) refer to jedec ms - 012 for complete dimensions and notes. all dimensions in millimeters . soic package marking scheme legend: x xx xxx= part number, p= package type (g=soic) r=rev code, lllllll= lot code ric=ramtron intl corp, yy=year, ww=work week example: fm 25l04b , green soic package, year 2010, work week 47 fm 25l04b - g a 00002g1 ric10 47 xxxx xxx - p r ll llll l ricyyww pin 1 3 . 90 0 . 10 6 . 00 0 . 20 4 . 90 0 . 10 0 . 10 0 . 25 1 . 35 1 . 75 0 . 33 0 . 51 1 . 27 0 . 10 mm 0 . 25 0 . 50 45 ? 0 . 40 1 . 27 0 . 19 0 . 25 0 ? - 8 ? recommended pcb footprint 7 . 70 0 . 65 1 . 27 2 . 00 3 . 70
fm25l04b - 4kb 3v spi f - ram rev. 3.0 jan. 2012 page 13 of 14 8 - pin tdfn (4.0mm x 4.5mm body, 0.95mm pitch) note: all dimensions in millimeters . the exposed pad should be left flo ating. tdfn package marking scheme for body size 4.0mm x 4.5mm legend: r=ramtron, g=green tdfn package , xxxx=base part number llll= lot code yy=year, ww=work week example: green/rohs tdfn package, fm25l04b, lot 0003, year 2011, work wee k 07 r 5l0 4 b 0003 1107 rg xxxx llll yyww pin 1 4 . 0 0 0 . 1 4 . 50 0 . 1 0 . 75 0 . 05 0 . 40 0 . 05 0 . 95 0 . 20 ref . pin 1 id 0 . 0 - 0 . 05 2 . 85 ref 3 . 60 0 . 10 2 . 6 0 0 . 1 0 exposed metal pad should be left floating . 4 . 30 0 . 45 0 . 95 recommended pcb footprint 0 . 60 0 . 30 0 . 1
fm25l04b - 4kb 3v spi f - ram rev. 3.0 jan. 2012 page 14 of 14 revision history revision date summary 1.0 11/10/2010 initial release 1.1 12/15 /2010 fixed endurance section on pg 8. 1.2 1/31/2011 added esd ratings. 1.3 2/15/2011 updated dfn package marking. changed t pu and t vf spec limit s. 3.0 1/6/2012 changed to production status. changed t vf spec.

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